                 Release Note for BCM5705 BOOT Code Firmware
             ==================================================
                    
Starting this version 3.23, all 5705 family devices will unify the version number.
The new release text is moved to shared file, releases.txt. Please refer to that
file for new the release note.

Version 3.22: 

  1. Writes firmware id to shared memory rx_cpu_firmware_id field
  
    Enhancement:
      Phase1 & Phase2 code will write the firmware id to rx_cpu_firmware_id.
      
    Eng. Notes:
      bootcode phase1 will write value 0xfefe0008 to shared memory 0xc0c.
      bootcode phase2 will write value 0xfefe0009 to shared memory 0xc0c.
      When phase2 executes properly, the value phase1 wrote should be
      overwritten by phase2 code.  
      
Version 3.21:

  1. Changed device id form 0x1653 to 0x1654
  
    Problem:
      We need new device id for A2/A3 devices.
      
    Cause:
      The default was set to A0/A1 (0x1653) devices, and more customers
      need A2/A3 version bootcode.
    
    Fix:
      Changed device id. 

Version 3.20:

  1. Restored phy type in manufacture data block
  
    Problem: 
      PXE code needed this field to determine the phy type
    
    Fix: 
      Hard coded this field to be copper type
                     
Version 3.19:
  
  1. Removed TX CPU access
  
    Problem: 
      There was an access to TX CPU before halt instruction.
      
    Cause:   
      When there is no main power and WOL is disabled, the CPU will intend 
      to shutdown itself to save power. Before the halt instructionm, 
      there was an access to TX CPU to halt TX CPU, which does not exist 
      in 5705/Shasta family device.
      
    Fix:     
      Removed the TX CPU access.
      
    impact:  
      none
    
  2. Reserved more space for stack area.
  
    Problem: 
      Incoming data could potentially corrupt the phase1 bootcode before 
      loading 2nd phase bootcode is done. 
      
    Cause:   
      After initializing mbuf address, size registers and posting the 
      signature, the phase1 bootcode is still active and busy loading 2nd 
      phase bootcode. Before the 2nd phase loading is complete, and if 
      there is data coming in, it may corrupt the phase1 bootcode.
      
    Fix:     
      Increased stack size area to 4K which will cover the area of phase1
      bootcode.           
                 
Version 3.18: 

  1. Fixed WOL issue
    
    Problem: 
      After using restart option in Windows and restart computer to DOS. 
      Then, turn off the power, WOL will not work.

    Cause:   
      Since there was no power lose from Windows to DOS, the signature 
      deposited by driver was not cleared. Therefore, when power lose from 
      DOS, bootcode sees the WOL signature and was bypassing the WoL 
      initialization.
      
    Fix:     
      Changed bootcode to clear WoL signature if the startup does not have 
      driver signature.
      
Version 3.17: 

  1. Get phy id from phy register instead of NVRAM configuration

    Enhancement: 
      Get phy id from phy register instead of NVRAM configuration

    Cause:
      Originally, the phy id field in shared memory was read from NVRAM
      configuration. User could changed it any way they wanted and
      driver cannot rely on the content to perform as correct judgements

    Change:
      The phy id in shared memory will be read from phy register instead
      of NVRAM field.

  2. Removed Phy 1.8v option
  
    Problem:
      Earlier bootcode contains 5701 product code which will
      cause a glitch in the PHY clock and could cause PHY to lock-up. 
      
    Cause:
      The code was carry over from 5701 in the old day was not needed
      in newer product.
    
    Fix: 
      Removed unnecessary code that could cause Phy to lock-up.

  3. Added workaround for VPD glitch

    Problem:
      A false glitch can happen intermittently when host is accessing MII
      registers.

    Cause:
      For new rev. chip, the lay out was too close between MII signals
      VPD event signal that may cause crosstalk. 

    Fix:
      Put a double read for VPD event. If the event self clears without
      firmware acknowledge, it is hardware glitch.


 Version 3.16:

  1. Applied specific application change

    Problem: 
      On a specific application, when the laptop was not docked, link
      was not desirable to go to giga bit speed.

    Cause:
      It was laptop design issue with transformer usage. 
      
    Fix:
      Using GPIO2 to indicate the laptop docking status. When docked,
      use giga bit speed. When not docked, use 10/100.
      
Version 3.15: 

  1. Lower voltage for 2.5v.
  
    Problem: the actual 2.5v regulator output is 2.66v.
    Cause:   The actual voltage level is higher than the specification
             indicates.
    Fix:     Changed the regulator setting to lower the voltage. 


  2. Enable phy in cold reset.

    Problem: 
      Cannot access MAC register if phy is in powerdown state. 
      
    Cause:   
      When Windows is restarting, the driver go through the shutdown 
      routine. When WoL is disabled, it turns off phy completely by 
      putting phy to powerdown mode. When it restarts, the main power,
      3.3 volt is stable. Only rely on PCI reset, the device does not
      generating power on reset; thus phy is not reset and still in 
      powerdown state. To access MAC registers, phy clock is required and
      we need to access the register for MAC address initialization.
      
    Fix:     
      If it is cold reset, it will put phy to 10mbps to enable the clock 
      before accessing MAC registers. This also helps to reduce power 
      consumption by putting at lowest speed. The phy will eventually get 
      reset at phase 2 code.
             
Version 3.14:

  1. Changed SEEPROM clock speed from 148 Khz to 374 Khz.

    Problem: The SEEPROM clock speed was set to 148KHz, in which, resulted
             in longer 2nd phase bootcode loading time. 
    Cause:   The specification did not indicate the source frequency to be 
             used to generate SEEPROM clock. The bootcode was using core 
             clock, same as 5702/3/4, for the calculation of the frequency.
    Fix:     The bootcode bypassed the initialization and using hardware
             default speed of 374 Khz. 

Version 3.13: 

  1. Changed default VPD data string from "5782" to "5705"

    Problem: The VPD data default seting was set to 5782 instead of 5705
    Cause:   The file gen_nic_mfg3.c was shared by 5782 project. When 
             the string was Changed in 5782 project, the string also got 
             changed in 5705 project. 
    Fix:     The file is separated between projects. Now each project has
             it's own copy of gen_ic_mfg3.c.
   
Version 3.12:

  1. Use default setting as 1.2V voltage for A1 and later.
  
    Problem: The core 1.2V voltage was set to 1.38V.
    Cause:   The chip revision A0 had a bug that the core voltage was too
             low, to workaround this problem, the bootcode was programming
             the core voltage higher.
             In A1 revsion, the problem is fixed in hardware; however, the
             bootcode was still programming the higher voltage. As result,
             the voltage was set to 1.38V, higher than legal voltage.
    Fix:     Bootcode will program higher voltage for revision A0 chip only.
             For A1 and later, it will use hardware default value. 

  2. Fixed PXE ROM size bug

    Problem: The secfg option 29, expansion ROM size was not taking effect.
    Cause:   Bootcode did not program the correct value in the register.
    Fix:     Bootcode is changed to program correct expansion ROM size
             setting in NVRAM configuration into register.

  3. Moved ClockRun enable code to the beginning of config access

    Problem: The PCI config space register cannot be access correctly when
             ClockRun is disabled and the BIOS had ClockRun feature 
             turned on.
    Cause:   When BIOS enables ClockRun feature, the miniPCI bus clock
             stops until ClockRun signals is asserted by device. Without
             enabling ClockRun in device, there is no PCI clock and
             bootcode has no access to PCI config space. 
    Fix:     The problem cannot be fixed in bootcode because the ClockRun
             enable bit itself is in PCI config. space.
             The change here is to move the enabling ClockRun at earlier
             time, before any config space access, and hoping (by luck) 
             there is an activities on the bus to trigger the bootcode 
             write successfully to reduce the chance of subsequence 
             incorrect access.

  4. Fixed LED problem with Windows standby when WOL is disabled
  
    Problem: When Windows goes to standby with WOL disabled, the LED will
             be half way turned on.
             
    Cause:   CPU attempt to slow down the clock when there is no main power. 
             To slow down the clock, we had to access clock control PCI 
             configuration register, 0x74, the CPU hangs. This means, it was 
             not able to power down the chip. For some reasons, with hang 
             state and power supply to the chip, it driven LED on. 
 
    Fix:     CPU skipped slow down clock routine when there is no main power
             and powered-down the chip properly. With no power to the chip, 
             it would not drive LED on. 

Version 3.11:
    1. Turned off Instruction Cache. (fixed ASF problem, CQ#6516)

Version 3.10:
    1. Fixed LED problem for WoL

Version 3.09:
    1. Supports Shared Memory data structure version 1
    2. Removed phase 2 image loading failure LED blink feature (to save space)
    3. Enabled RX CPU Instruction/data cache (to improve perfomance)
    4. Use 16 word NVRAM access for PXE

Version 3.08:
  1. Added PXE loading fix.
  2. Added Workaround for Errat#19. (DAC trim default values need to increase 4%)
  3. Fixed phy power down problem (ClearQuest 6001)
  4. Supports A1 revision silicon
  5. Changed phy type always to be copper
  
    Problem: 
      User could change phy type in NVRAM configuration to serdes and 
      cause the bootcode to misbehave
             
    Cause:   
      Originally, the bootcode was shared between copper and Serdes 
      verion; therefore, we needed a configuration field to indicate if 
      this is copper or serdes. Today, we separated the bootcode image 
      already, we don't need to use this configuration any more.
              
    Fix:
      Instead of reading phy type from configuration, it now will always 
      force this field to be copper type. 

Version 3.07:
    1. Support WoL Limit 10 speed
    2. Added second phase signature to fix WoL that stuck in 1G problem
    3. Fixes various ASF problems (flooding the network, not able to send PET).
       - add code to clear TxMbuf content
       - add code to enable mbuf manager

Version 3.06:
    1. Added CardBus support.
    2. Fixed stack overflow problem when ASF is enabled.

Version 3.05:
    1. Changed to force CLKRUN to maintain PCI clock for Mini-PCI mode.

Version 3.04:
    1. Fixed a problem where system can be waken up with a broadcast 
       packets with zero data content.
    2. Programed internal voltage regulator to raise voltage from 1.23V to 
       1.24V.

Version 3.03:
    1. Changed to disable Auto powerdown feature by default.

Version 3.02:
    1. Changed to allow user to enable/disable Auto powerdown GPHY.

Version 3.01:
    1. Changed to program optimum value for voltage regulator.

Version 3.00:
    1. Changed to enable CLKRUN output when it's in Mini-PCI mode.

Version 2.27:
    1. Fixed a problem where OOB WOL doesn't work.

Version 2.26:
    1. Implemented a new WOL scheme that requires drivers released
       after 07/17/02. Legacy drivers will continue to behave according 
       to the old scheme.
    2. Added power saving mode support.
    3. Fixed State Reg. 2nd stage boodcode override bug.
    4. Fixed WOL when power down from PXE or DOS driver.
    5. Fixed the timing on the ASF enable information propagation.
    6. Added workaround for ATMEL flash corruption problem.
    7. Fixed driver/bootcode race condition on MII register read problem.
    8. Turned VAUX off when WoL is disabled at standby power.
    9. Turn on GPHY.
   10. Changed to reserve memory for ASF firmware when it's enabled.

Version 2.25:
    1. Fixed PXE speed bug
    2. Added PCIX State Reg. RETRY_SAME_DMA workaround
    3. Fixed a problem where it doesn't load ASF.

Version 2.24  :
    1. Fixed a problem where system is locked if PXE is enabled.

Version 2.23  :
    1. Initial release for BCM5705.

