      Jade/Caesar Selfboot Patch For Chip Rev. A2
      -------------------------------------------
            5787, 5787m, 5787f, 5754, 5754m

 ----------------------------
 Version 2.09 ---- 11/13/06 
----------------------------
1. Compiler Error

  Problem: CQ#27433
    NIC is no longer recognized by b57diag and Windows after update selfboot 
    version 2.08.
    
  Cause:
    The compiler for version 2.08 was not completed for 5787/5787f/5754/5754m.
    This incorrect image will cause device disappeared after download.
    
  Notes:
    Version 2.08 was removed from release directory.
 
    

 ----------------------------
 Version 2.08 ---- 11/09/06 
----------------------------
1. PCIE Link Polarity

  Enhancement: CQ#27039, CQ#26767, CQ#27105, CQ#26588
    Apply PCIE Link polarity workaround only at hardware reset (POR or 
    PEReset). 

2. Improve PCIE SerDes PLL Power Down Feature in conjunction with clkreq being enabled. 
  
  Enhancement: CQ#27236 
    Poll the actual clkreq state at 0x68A4[2]: 
    a. If 0x68A4[2]=1, then enables PLL power down by writing 0x7d54 with 0x7000. 
    b. if 0x68a4[2]=0 and port is link down, then disables PLL power down by 
    writing 0x7d54 with 0x7080. 
  
  Note: 
    This enhancement is only applicable to 5787M.
    Need to use version 10.05.04 or later version of b57diag program to enable/disable
    this feature. 


3. Increase the Fast Training Sequence(FTS) timming
 
  Problem: CQ14315
    If L0s is enabled on the BRCM chip a "yellow bang", or a system hang 
    condition can occur.
    
  Cause:
    During the L0s to L0 exit transition, symbol lock can be lost if the 
    system reference clock has not fully stabilized what leads the PCI-E 
    link training state machine to go through the "detect" state.  Going 
    through "detect" causes an internal reset to the BRCM chip what causes 
    "yellow bang" and/or a system hang condition based on the chipset 
    configuration.
    
  Fix:
    1. Change Serdes RX Timer from 768 ns to 2 uS to make sure the 
       Serdes CDR is stable before it sends data to the Physical Layer.  
    2. Increase FTS Count from 1uS to 2.25 uS to avoid intermittent GRC 
       Reset when L0s is enabled.
  
    Since RX Timer value and FTS Count change only needed before PCIE link 
    training, bootcode will initialize those values and retrain the PCIE 
    link during cold reset only. When driver reset, this workaround is 
    bypassed to avoid PCIE link retrain. 
    
  Impact:
    Increasing the amount of FTS required to transition from L0s to L0, 
    performance impact between 1uS to 2.25uS is un-noticeable.
     
     
                 

----------------------------
 Version 2.07 ---- 10/10/06 
----------------------------
1. L1 exit latency improvement
 
  Enhancement: CQ#27044
    Improve the L1 exit latency when Clock Request is enabled.
    
  Note:
    No change for non-Mobile parts.


2. Enable Clock Request
 
  Enhancement: CQ#26951
    The clock request was disabled in version 2.06 for CQ #26629. 
    Change to use h/w default setting.
     

----------------------
Version 2.06  9/20/06
----------------------
1. Disable Clock Request
 
  Enhancement: CQ#26629
    The clock request enabled feature is not fully tested. This feature needs 
    to be disabled for RC 10.0 release.
    
  Note:
    The ClockReq is automatically disabled by h/w on a non-Mobile parts; therefore,
    this change does not affect non-Mobile parts.
    

----------------------
Version 2.05  8/18/06
----------------------
1. Removed disabling of ClkReq.

  Enhancement: CQ26097
    Per project lead's decision, the feature was disabled before validation.
    However, without enabling it, PQA will not be able to test it. Therefore,
    we will enable this feature. 
  
  Change:  
    The change is made so firmware will not touching register 0xdc. The value
    to advertise ClkReq feature will be based on the hardware default.
    The ClkReq is enabled only in Mobil devices. 
    
  Impact:
    Bootcode's change may also get over written. Updated driver should be used
    to ensure the function is enabled. (Refer to CQ26098 to find out the
    correct driver version that address this issue.)  
 
2. Cable Sense Support

  Problem:
    The GPhy was shutdown even if the cable sense mode is enabled.
    
  Cause:
    Coding error
    
  Fix:       
    Changed the code so it does not power down the Gphy if cable
    sense mode is enabled.
    

----------------------
Version 2.04  3/31/06
----------------------
1. Changed SSID
 
  Enhancement: CQ#23848
    For Jade devices, bit-15 of SSID needs to be set to 1.
    There is no impact/change for Caesar devices.     

2. Initialized Cardbus pointer register

  Enhancement: CQ#23431
    Since Cardbus support is no longer a requirement, in order to pass
    the plug-fest compliance test, we write zero to register 0x28 to disable
    cardbus feature.

----------------------
Version 2.03  2/09/06
----------------------
1. Enable PEReset Mask
 
  Problem:
    CQ#23039:
      On certain systems, when entering S5 state (with WoL enabled), the 
      LOM current draw on the 1.2V rail can fluctuate between ~90mA and 
      ~150mA from shutdown to shutdown.

    CQ#22684:
      On certain systems (with WoL enabled), the 5754/A1 LOM may disappear 
      during repeated S5 Power-Cycle tests.
 
  Cause:
    As part of the bootcode f/w logic, the NIC f/w will make access to 
    certain registers (0x00-0xff and 0x7c00-0x7fff) when the firmware 
    detected that the Vmain power goes low.  Due to CQ23039, the register 
    bit that the firmware used for detecting the "Vmain power state" can 
    also toggles between logical '0' and '1', and this leads to f/w to not 
    able to make reliable read/write access to the registers (0x00-0xff and 
    0x7c00-0x7fff), which ultimately causes bad behaviors that is described 
    in CQ22684.
 
  Fix:
    Firmware now enables the PEReset Mask register bit (0x68a4[16]=1).  By 
    enabling this register bit, the chip exits the reset state after the 
    current fluctuation become stabilized, which eliminates the toggling of 
    the "Vmain power" detection register bit, which ultimately enables 
    successful access to the register (0x00-0xff, 0x7c00-0x7fff) by the f/w.
 
  Impact:
    Fixes CQ#23039 and CQ#22684.

----------------------------
 Version 2.02 ---- 1/24/06
----------------------------
1. Changed CQ#22832 fix

  Problem: CQ#22832
    The CQ#22832 request to change 0x7d00 access to read-modify-write still
    have problem on some system when reference clock is not stable. 
    
  Cause:
    Absolute-write may corrupt register 0x7D00 content under corner conditions.
    
  Fix:
    Changed to code to not to touch 0x7d00 at all. 
    
  Impact:
    There is no impact if the WOL feature is not enabled in our device. There
    is also no impact if the system always broadcasts PME_Turn_Off tlp message
    to downstream before it removed the main power in system OOB or hibernate 
    scenario.  
    
    There is little power consumption increase when a) WOL is enabled in our 
    device and b) the system ungracefully removes the main power without 
    sending out PME_Turn_Off tlp message to downstream in system OOB or 
    hibernate scenario. The current draw in our device is measured at 236mA 
    as compared to 172mA before this change. 
    
    Since there is no more 0x7d00 access, version 2.01, #2 (Enabled ASIC 
    fix for CQ#11011), is undone. Using hardware default value. 

2. Enabled ASIC fix for tx Ethernet packet corruption on late collision

  Enhancement: CQ#22908, CQ#14561, CQ#14521
    Since the ASIC is fixed and verified by ASIC team, we are enabling the
    fix in this version.
    
----------------------
Version 2.01  1/18/06
----------------------
1. Changed 0x7d00 access to absolute write

  Problem: CQ#22832
    A value of 0xa000 was left in register 0x7d00 and caused the device to 
    disappear in some systems.
    
  Cause:
    When the device was put into D3 power state, due to the clock issue, the 
    PCIE registers become not accessible. If read-modify-write were used at
    this point, the read will fail and returning zero to CPU. Then, after
    CPU modify the content and write back, many critical bits are cleared in
    register 0x7d00. As result, the subsequence reset, the device could not
    establish PCIE link and disappears from the host. 
    
  Fix:
    Changed 0x7d00 register to absolute write instead of read-modify-write.
    
2. Enabled ASIC fix for CQ#11011

  Enhancement:
    The decision has been made to enable this ASIC fix to be consistent with
    Shasta/Baxter. This is done by clearing bit 18 of 0x7d00.
    
3. Removed clkreq advertisement

  Enhancement: CQ#22829
    Until ASIC teams verifies this function, we will disable feature for now.
   
------------
Version 2.00
------------
Initial ASIC A2 patch release    
